India's Semicon 2.0 Targets 3nm Chip Tech in 8 Years With Rs 1.27 Lakh Crore Plan

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India's IT Minister Ashwini Vaishnaw announced in late August 2026 that the country aims to develop 7nm to 3nm chip technology within eight years under Semicon 2.0, a government program approved with a Rs 1,27,500 crore outlay. The plan covers chip design, equipment, materials, packaging, R&D, and talent development across six pillars, but is a technology roadmap rather than a manufacturing milestone. India's only operational fab, SCL Mohali, currently produces chips at around 180nm, and the country's first major commercial fab — a Tata-PSMC joint venture in Dholera, Gujarat — remains under construction targeting mature nodes, with commissioning expected in 2028. The government's claim of possessing '40nm technology' refers to design capability and process knowledge gained through partnerships, not commercial wafer production at that node. On the talent front, around 70,000 students across 332 universities have received chip-design training, and 23 design projects worth over Rs 803 crore have been sanctioned under the Design Linked Incentive scheme.

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