Why the Same Code Breaks on ARM but Not Intel: Store-Load Reordering Explained

A recurring bug pattern emerges when engineering teams migrate code from Intel x86 to ARM64 processors: data corruption or deadlocks appear on ARM despite the code working flawlessly on Intel hardware. The root cause is store-to-load reordering, a behavior where CPUs execute memory operations out of program order to keep pipelines busy, using a store buffer that delays writes to cache. While x86 processors mask this reordering due to their stricter memory model, ARM64 exposes it, making previously hidden concurrency bugs observable. A simple two-thread litmus test demonstrates that both threads can read zero from shared variables simultaneously — an outcome that sequential logic says should be impossible. Inserting a proper CPU-level memory fence instruction, such as 'mfence' on x86 or 'dsb sy' on ARM64, restores the expected behavior by preventing loads from bypassing pending stores.