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Why Custom AI Chips Like TPUs Beat GPUs at Scale but Struggle With Low-Batch Tasks

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Purpose-built AI accelerators such as Google's TPUs differ fundamentally from GPUs by sacrificing general programmability to maximise matrix multiplication efficiency, freeing up silicon area for more compute units and on-chip memory. Their core architectural feature, the systolic array, reuses data across a grid of multiply-accumulate cells, dramatically improving the ratio of floating-point operations to memory bandwidth. However, this specialisation comes with a structural weakness: small or irregularly shaped matrix operations leave processing cells idle, unlike GPUs which can repurpose their lanes more flexibly. The efficiency gap is widest during high-throughput batch inference and narrowest at batch size one, such as single-token generation in language models. Because the economics of custom chip design require massive scale to recover fixed costs, this silicon typically exists as cloud capacity rather than a purchasable component, meaning buyers are effectively evaluating a hosted service.

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