TSMC and NYCU develop 0.42nm interface to boost MoS2 transistor performance

Researchers from National Yang Ming Chiao Tung University and TSMC have jointly developed a new interface design for next-generation atomically thin transistors. The team engineered a 0.42-nanometre aluminium oxide layer positioned between a monolayer of molybdenum disulfide (MoS2) and a hafnium oxide dielectric material. This ultra-thin insulating layer serves as a critical interface in the transistor architecture. The design successfully preserves strong electrical control and efficient carrier transport despite the extremely thin dimensions involved.