Three Common STM32 Timer Mistakes That Cause Incorrect PWM Output

Developers working with STM32 microcontrollers often encounter incorrect PWM frequencies despite seemingly correct PSC and ARR register values. A key source of error is off-by-one miscalculations, since both PSC and ARR are zero-based registers, meaning PSC=71 acts as a divide-by-72 prescaler. Another frequent mistake involves using the CPU or APB peripheral clock instead of the actual effective timer input clock, which varies by device family and clock tree configuration. Additionally, choosing PSC and ARR values without considering counter resolution can affect duty-cycle precision, as a larger ARR provides more discrete compare values. The correct formula for edge-aligned PWM frequency is timerClock divided by the product of (PSC+1) and (ARR+1), and consulting the specific MCU reference manual remains essential for accurate results.