Packaging, Not Transistor Size, Now Limits Advanced Chip Production

The industry has reached a physical ceiling: lithography tools can expose a field of roughly 26 by 33 millimetres in one pass, which caps the size of a single die. Because defect probability grows exponentially with die area, very large dies become economically unviable, pushing designers to split functions into smaller chiplets. These chiplets must then be linked through advanced packaging, which has become the scarce resource in the supply chain. Packaging capacity expands slowly because assembly involves multiple specialised, separately qualified steps, so constraints show up as allocation rather than price.