How RISC-V Loads a 32-Bit Value Using Two Instructions Instead of One

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RISC-V (RV32I) and x86 (i386) differ fundamentally in instruction set size and encoding: x86 supports 1,000–1,500 variable-length instructions, while RV32I has roughly 40 fixed 4-byte instructions. Because every RISC-V instruction must fit in exactly 32 bits, there is no room to encode a full 32-bit immediate value alongside an opcode and register field in a single instruction. To load a 32-bit constant, the assembler splits the operation into two real instructions — LUI to place the upper 20 bits and ADDI to add the lower 12 bits. The familiar 'li' (Load Immediate) command is actually a pseudo-instruction that the toolchain silently converts into this two-step sequence. A further complication arises because ADDI sign-extends its 12-bit field, so the assembler must automatically increment the upper 20-bit value when the lower 12 bits would otherwise be interpreted as negative.

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