How an FPGA's Building Blocks Work, Illustrated with the Tang Nano 9K

An explainer walks through the core parts of an FPGA for developers coming from microcontrollers like Arduino or ESP32, stressing that designs describe circuits rather than sequential programs. It covers input/output blocks around the chip's edge that control pin direction, drive strength, and voltage standard, and notes that a 3.3 V pin may still need a level shifter to drive 5 V devices. Configurable logic blocks use lookup tables and flip-flops rather than fixed gates, with a carry chain for fast adders. The configuration lives in SRAM and is reloaded from flash at power-up, which the Tang Nano 9K's built-in flash makes nearly instant. The article also lists the GW1NR-9's resources and compares the current landscape, including low-cost boards and open-source tools, with the situation described in a 2013 EEVblog video.