Engineer Catches Hidden RTL Bug in AXI Spec Two Weeks Before Chip Tapeout

A hardware verification engineer discovered a critical latent bug in an AXI interconnect project just two weeks before tapeout, despite the design having passed over 500,000 simulation cycles and achieving more than 98% code coverage. The issue surfaced when a senior architect questioned what would happen if the AWLEN parameter wrapped around 256 during an INCR burst — a scenario the protocol spec left as undefined behavior. Because the testbench had been configured to skip undefined sequences, a state machine hang in the RTL had gone undetected throughout the verification process. The incident highlighted that verification must go beyond confirming the RTL matches the spec, and should also validate that the spec itself is complete and correct. The engineer concluded that the most critical skill in chip verification is not tool expertise, but knowing which edge-case questions the specification authors may have overlooked.